Inductance model and analysis methodology for high-speed on-chip interconnect

With operating frequencies entering the multi-gigahertz range, inductance has become an important consideration in the design and analysis of on-chip interconnects. In this paper, we present an accurate and efficient inductance modeling and analysis methodology for high-performance interconnect. We determine the critical elements for a PEEC based model by analyzing the current flow in the power grid and signal interconnect. The proposed model includes distributed interconnect resistance, inductance and capacitance, device decoupling capacitances, quiescent switching currents in the grid, pad connections, and pad/package inductance. We propose an efficient methodology for extracting these elements, using statistical models for on-chip decoupling capacitance and switching currents. Simulation results show the importance of various elements for accurate inductance analysis. We also demonstrate the accuracy of the proposed model compared to the traditional loop-based inductance approach. Since the proposed model can consist of hundreds of thousands of RLC elements, and a fully dense mutual inductance matrix, we propose a number of acceleration techniques that enable efficient analysis of large interconnect structures. We use block-diagonal matrix sparsification that guarantees the passivity of the sparsified circuit while maintaining good accuracy. We also employ reduced-order modeling using the PRIMA algorithm. To accelerate the reduced order modeling, we introduce a new formulation of the moment calculation that employs a matrix reduction technique and also ensures that the resulting matrix is positive-definite. This allows the factorization of this matrix to be performed using efficient Cholesky factorization instead of the more time consuming LU decomposition, traditionally used. The proposed methods were implemented and used on the clock network of a gigahertz microprocessor. The combined sparsification and reduced order modeling approaches allow the analysis of a circuit model consisting of over 720 thousand RLC elements and 8 million mutual inductances in less than 1 hour. The presented analysis results emphasize the importance of inductance on the signal behavior in high performance processor designs and demonstrate the accuracy and efficiency of the proposed inductance model and analysis methodology.